OPEN TO ASIC / FPGA / VLSI / RTL ROLES
RTL Design Engineer▌
Electronics & Communication Engineering graduate who builds digital hardware from the transistor up — a single-cycle RISC-V core, ASIC RTL migrated at ISRO, and encryption hardware benchmarked across three architectures. I like problems where the correct answer is provable, not just plausible.
I'm an ECE graduate from BMS College of Engineering, Bengaluru, having completed my degree in 2026. Most of my time goes into RTL — writing it, verifying it, and figuring out what happens to it once it leaves Verilog and becomes silicon. That curiosity took me to ISRO's satellite centre, where I spent a summer migrating FPGA logic into synthesizable ASIC blocks.
Outside of internships, I build things to understand them properly: a RISC-V core to see how an instruction actually becomes a signal, three versions of AES to see what changes when you trade area for throughput, a CMOS adder in LTSpice to see the delay numbers stop being theoretical.
Architected a single-cycle RV32I core in Verilog — full datapath (PC, register file, ALU, immediate generator) coordinated by a centralized control unit. Verified 100% instruction coverage of the base ISA with a custom testbench simulating end-to-end execution.
Three pipelined AES variants with memory-based S-Boxes, each round decomposed into independent stages. Synthesized on Vivado and benchmarked across LUTs, timing, power, throughput.
Built from cascaded full-adder CMOS cells across 45nm and 180nm nodes. The 45nm node came in 84% lower area, 62% lower power, and 70% lower delay per bit — at up to 2.4x the frequency.
Embedded system using PIR and temperature sensors to drive real-time seat allotment and automated climate control, cutting standby power draw. Published as an IEEE conference paper.
IMU-based orientation feedback and ultrasonic obstacle avoidance, with Google API + Pushover integration delivering location-tracked SOS alerts within 5 seconds of activation.